######################################################################
# Bit serial subtractor ModelSim do file
# Stephen West, James Carroll
# BYU ECEn 620, Fall 2008
######################################################################
quit -sim
vcom BitSerialSub.vhd

vsim BitSerialSub

add wave clk
add wave -color blue lsb_in
add wave a_in
add wave b_in
add wave carry_reg
add wave add1/*
add wave -color orange sub_out

force clk 1,0 10ns -r 20ns
#  01111 15
# -01111 15
# ------
#  00000  0

force a_in 1
force b_in 1
force lsb_in 1,0 20ns
run 20ns
run 20ns
run 20ns
run 20ns

force a_in 0
force b_in 0
run 20ns

#  111111 -1
# -111110 -2
# -------
#  000001 +1
force a_in 1
force b_in 0,1 20ns
force lsb_in 1,0 20ns
run 20ns
run 20ns
run 20ns
run 20ns

#  000001  1
# -111110 -2
# -------
#  000011 +3
force a_in 1,0 20ns
force b_in 0,1 20ns
force lsb_in 1,0 20ns
run 20ns
run 20ns
run 20ns
run 20ns

#  000001  1
# -111100 -4
# -------
#  000101 +5
force a_in 1,0 20ns
force b_in 0,1 40ns
force lsb_in 1,0 20ns
run 20ns
run 20ns
run 20ns
run 20ns

#  000001  1
# -111000 -8
# -------
#  001001 +9
force a_in 1,0 20ns
force b_in 0,1 60ns
force lsb_in 1,0 20ns
run 20ns
run 20ns
run 20ns
run 20ns
run 20ns

#  000001  1
# -001000  8
# -------
#  111001 -7
force a_in 1,0 20ns
force b_in 0,1 80ns
force lsb_in 1,0 20ns
run 20ns
run 20ns
run 20ns
run 20ns
run 20ns
force b_in 0
run 20ns
run 20ns
